1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more specifically, it relates to a synchronous SRAM supplied with two types of power supply voltages.
2. Description of the Background Art
A synchronous SRAM (static random access memory) mainly comprises two power sources for power supplied to an internal circuit and power for an input/output circuit deciding an input/output level. This is because a voltage optimum for the synchronous SRAM to keep a high speed itself and a voltage optimum for a logic chip of a CPU (central processing unit) or a chip set directly connected with the synchronous SRAM are different from each other.
More specifically, power Vdd for the internal circuit of the synchronous SRAM is generally 3.3 V (or 2.5 V as the case may be), and power VddQ for the input/output circuit is 2.5 V or 1.8 V. The power VddQ is equalized with a power supply voltage supplied to a peripheral logic chip of the synchronous SRAM. When the power VddQ is set to 2.5 V or 1.8 V, the synchronous SRAM the input/output level of the synchronous SRAM reaches a CMOS (complementary metal-oxide semiconductor) level of 2.5 V or 1.8 V (a high level is 2.5 V or 1.8 V, and a low level is 0 V).
As typical examples of such a synchronous SRAM, FIGS. 12 and 13 show a type 1 pipelined burst SRAM and FIGS. 14 and 15 show a synchronous network SRAM respectively. The synchronous network SRAM is an advanced standard synchronous SRAM in the process of standardization in JEDEC (Joint Electron Device Engineering Council). In the following description, pins and signals corresponding to the pins are denoted by the same reference numerals.
FIG. 12 illustrates the pin arrangement of the type 1 pipelined burst SRAM. Referring to FIG. 12, fifteenth, forty-first, sixty-fifth and ninety-first pins are power supply pins Vdd for an internal circuit, seventeenth, fortieth, sixty-seventh and ninetieth pins are ground power supply pins Vss for the internal circuit, fourth, eleventh, twentieth, twenty-seventh, fifty fourth, sixty-first, seventieth and seventy-seventh pins are power supply pins VddQ for an output buffer, and fifth, tenth, twenty-first, twenty-sixth, fifty-fifth, sixtieth, seventy-first and seventy-sixth pins are ground power supply pins VssQ for the output buffer.
Fifty-second, fifty-third, fifty-sixth to fifty ninth, sixty-second and sixty-third pins are data input/output pins DQa, sixty-eighth, sixty-ninth, seventy-second to seventy-fifth, seventy-eighth and seventy-ninth pins are data input/output pins DQb, second, third, sixth to ninth, twelfth and thirteenth pins are data input/output pins DQc, and eighteenth, nineteenth, twenty-second to twenty-fifth, twenty-eighth and twenty-ninth pins are data input/output pins DQd. Fifty-first, eightieth, first and thirtieth pins are parity data input/output pins DQPa, DQPb, DQPc and DQPd.
Thirty-second to thirty-fifth, forty-fourth to fiftieth, eighty-first, eighty-second, ninety-ninth and hundredth pins are address input pins A, and thirty-seventh and thirty-sixth pins are address input pins A0 and A1. An eighty-ninth pin is a clock input pin CLK. Ninety-second, ninety seventh and ninety-eighth pins are chip enable input pins CUE#, CE2 and CE1#. Eighty-third, eighty-fourth and eighty-fifth pins are burst control pins ADV#, ADSP# and ADSC#.
Eighty-eighth, eighty-seventh, ninety-third, ninety-fourth, ninetyfifth and ninety-sixth pins are write control input pins GW#, BWE#, BWa#, BWb#, BWc# and BWd#. An eighty-sixth pin is an output enable pin OE#, a sixty-fourth pin is a snooze mode (power sleep mode) input pin ZZ, a fourteenth pin is a flow-through input pin FT#, and a thirty-first pin is a linear burst input pin LBO#. Sixteenth, thirty-eighth, thirty-ninth, fortysecond, forty-third and sixty-sixth pins are non-connected pins NC.
FIG. 12 shows exemplary pin arrangement, and the forty-third non-connected pin NC is replaced with an address input pin in the case of 9 Mbits, for example. Further, any or all of the flow-through input pin FT#, the linear burst input pin LBO# and the snooze mode input pin ZZ may not be supported.
As shown in FIG. 13, the type 1 pipelined burst SRAM comprises control registers 21 and 22, a control logic circuit 23, logic circuits 27 and 28, a burst control logic circuit 24, an address register 25, a burst address counter 26, a memory cell array 30, a data input register 31, a data output register 34 and an output buffer 35.
The control register 21 captures burst control signals ADV# and ADSC# in synchronization with a clock signal CLK. The burst control logic circuit 24 captures a linear burst signal LBO# and the value of the control register 21 in synchronization with the clock signal CLK, and outputs an internal control signal for a burst operation.
The logic circuit 27 receives a burst control signal ADSP# and a chip enable signal CE1#. The logic circuit 28 receives chip enable signals CE1#, CE2 and CE3#.
The control register 22 captures outputs of the logic circuits 27 and 28 and write control signals GW#, BWE# and BWa# to BWd# in synchronization with the clock signal CLK.
The control logic circuit 23 receives the value of the control register 22, the output of the burst control logic circuit 24, an output enable signal OE# and a snooze mode signal ZZ and outputs a corresponding internal control signal.
The address register 25 captures addresses A0 to A16 in response to the output of the burst control logic circuit 24. The addresses A0 and A1 are output to the burst address counter 26. The burst address counter 26 outputs addresses Axe2x80x20 and Axe2x80x21 in response to control by the burst control logic circuit 24. A burst sequence (linear burst or interleaved) is selected with the linear burst signal LBO#.
The memory cell array 30 includes a plurality of memory cells arranged in rows and columns. A corresponding memory cell is selected on the basis of the output of the burst address counter 26 and the addresses A1 to A16 from the address register 25.
Data buses DBO to DB35 are provided in correspondence to the data input/output pins DQa (eight), DQb (eight), DQc (eight) and DQd (eight) and the parity data input/output pins DQPa to DQPd respectively.
The data input register 31 captures data from the data buses in response to control by the control logic circuit 23. The data input register 31 captures data from the data input/output pins DQa with the write control signal BWa#, data from the data input/output pins DQb with the write control signal BWb#, data from the data input/output pins DQc with the write control signal BWc# and data from the data input/output pins DQd with the write control signal BWd#. The data captured in the data input register 31 are written in the selected memory cell.
The data output register 34 captures data read from the selected memory cell in response to control by the control logic circuit 23. The output buffer 35 outputs the data captured in the output register 34 to the data buses in response to control by the control logic circuit 23.
All input signals excluding the linear burst signal LBO#, the output enable signal OE# and the snooze mode signal ZZ are captured in synchronization with the clock signal CLK.
36-bit write operations are controlled with the write control signal GW#. The write operations are executed byte by byte with the write control signals BWa# to BWd# and BWE#. A burst operation is controlled with the burst control signal ADSC# or ADSP#. The burst control signal ADV# controls a burst address. A read operation is initialized with the burst control signal ADSP#.
The overall chip enters a power down mode with the snooze mode signal ZZ, for saving a standby current.
FIG. 14 illustrates pin arrangement of the synchronous network SRAM. Referring to FIG. 14, fifteenth, sixteenth, forty-first, sixty-fifth, sixty-sixth and ninety-first pins are power supply pins Vdd for an internal circuit, seventeenth, fortieth, sixty-seventh and ninetieth pins are ground power supply pins Vss for the internal circuit, fourth, eleventh, twentieth, twenty-seventh, fifty-fourth, sixty-first, seventieth and seventy-seventh pins are power supply pins VddQ for an output buffer, and fifth, tenth, twenty-first, twenty-sixth, fifty-fifth, sixtieth, seventy-first and seventy-sixth pins are ground power supply pins VssQ for the output buffer. An eighty-fifth pin is a burst control/burst start input pin ADV/LD#. Eighty-seventh and eighty-eighth pins are a cock enable input pin CKE# and a read/write control input pin RIW#.
The arrangement of data input/output pins DQa to DQd and DQPa to DQPd, address input pins A, A0 and A1, a clock input pin CLK and chip enable input pins CE3#, CE2 and CE1# is identical to that shown in FIG. 12.
The arrangement of write control input pins BWa#, BWb#, BWc# and BWd#, an output enable pin OE#, a snooze mode input pin ZZ, a flow-through input pin FT# and a linear burst input pin LBO# is identical to that shown in FIG. 12. Thirty-eighth, thirty-ninth, forty-second, fortythird, eighty-third and eighty-fourth pins are non-connected pins NC.
FIG. 14 shows exemplary pin arrangement, and the eighty-third non-connected pin NC is replaced with an address input pin in the case of 9 Mbits, for example. Further, any or all of the flow-through input pin FT#, the linear burst input pin LBO# and the snooze mode input pin ZZ may not be supported.
As shown in FIG. 15, the synchronous network SRAM includes control logic circuits 41 and 43, a control register 42, a logic circuit 44, an address register 45, a burst address counter 46, write address registers 47 and 48, multiplexers 49 and 53, a memory cell array 30, data input registers 51 and 52, a data output register 54 and an output buffer 55.
The control logic circuit 41 receives a clock signal CLK and a clock enable signal CKE# and outputs an internal clock K. The logic circuit 44 receives chip enable signals CE1#, CE2 and CE3#.
The control register 42 captures an output of the logic circuit 44, a burst control/burst start signal ADV/LD#, a read/write control signal R/W# and write control signals BWa# to BWd# in response to the internal clock K.
The control logic circuit 43 receives outputs of the control register 42, an output enable signal OE# and a snooze mode signal ZZ and outputs a corresponding internal control signal.
The address register 45 captures addresses A0 to A16 in synchronization with the internal clock K. The addresses A0 and A1 are output to the burst address counter 46. The burst address counter 46 outputs addresses Axe2x80x20 and Axe2x80x21 in response to a linear burst signal LBO#. A burst sequence (linear burst or interleaved) is selected with the linear burst signal LBO# for deciding the values of the addresses Axe2x80x20 and Axe2x80x21.
The write address register 47 captures the addresses A2 to A16 output from the address register 45 and the addresses Axe2x80x20 and Axe2x80x21 output from the burst address counter 46 in response to the internal clock K. The write address register 48 captures the value of the write address register 47 in response to the internal clock K.
The multiplexer 49 selectively outputs the values of the burst address counter 46 and the address register 45 or the value of the write address register 48 on the basis of control by the control logic circuit 43. A corresponding memory cell of the memory cell array 30 is selected on the basis of the output of the multiplexer 49.
The data input register 51 captures data from the data buses in synchronization with the internal clock K in response to control by the control logic circuit 43. The data input register 52 captures the data from the data input register 51 in synchronization with the internal clock K in response to control by the control logic circuit 43. The data captured by the data input register 52 are written in the selected memory cell.
The data output register 54 captures data read from the selected memory cell in synchronization with the internal clock K. The output buffer 53 outputs the data captured by the data output register 54 to the data buses in response to control by the control logic circuit 43.
All input signals excluding the linear burst signal LBO#, the output enable signal OE# and the snooze mode signal ZZ are captured in synchronization with the clock signal CLK.
Read and write operations are initialized with a burst control signal ADVILD#. The read or write operation is executed with a read/write control signal R/W#. Data are written byte by byte with the write control signals BWa# to BWd#.
While each of FIGS. 13 and 15 illustrates a single output buffer, 36 output buffers are provided in correspondence to the data buses DB0 to DB35 respectively in practice.
All input buffers (included in the control register 21, the address register 45 etc., for example) capturing the input signals are supplied with a power supply voltage VddQ from the power supply pins for the output buffers.
The aforementioned synchronous SRAM has two power sources for power Vdd for an internal circuit and input/output power VddQ. In general, the power Vdd is 3.3 V and the power VddQ is 2.5 V.
In this case, a standard high input/output level is the VddQ level and a standard low input/output level is 0 V. FIG. 16 shows an input buffer 90 employed for capturing an input signal.
The input buffer 90 shown in FIG. 16 includes PMOS transistors TP1 and TP2 and NMOS transistors TN1 and TN2. The transistors TP1 and TN1 are serially connected between the power VddQ and a ground power source, and the gates thereof receive the input signal. The transistors TP2 and TN2 are serially connected between the power VddQ and the ground power source, and the gates thereof are connected to a node N1 between the transistors TP1 and TN1.
A shift latch 92 includes PMOS transistors TP3 and TP4 and NMOS transistors TN3 and TN4. The transistors TP3 and TN3 are serially connected between the power Vdd and the ground power source. The transistors TP4 and TN4 are serially connected between the power Vdd and the ground power source. The gate of the transistor TN3 is connected to a node N2 between the transistors TP2 and TN2, and the gate of the transistor TP3 is connected to a node N4 between the transistors TP4 and TN4. The gate of the transistor TN4 is connected with the node N1, and the gate of the transistor TP4 is connected with a node N3 between the transistors TP3 and TN3. A signal from the node N4 is input in an internal circuit (not shown).
The input buffer 90 receives a signal of the CMOS level of 2.5 V in a CMOS inverter supplied with the power VddQ. The shift latch 92 amplifies an output of the input buffer 90 to the CMOS level of 3.3 V and transmits the amplified output to the internal circuit. When employing the input buffer 90, no through current flows since the CMOS inverter supplied with the power of 2.5 V receives the input signal of 2.5 V.
However, the aforementioned synchronous SRAM has a possibility of causing a malfunction as described below. This problem is now described.
In the aforementioned synchronous SRAM, 36 output buffers (referred to as output buffers 6#0 to 6#35) are connected with the power VddQ. FIG. 17 shows paths for supplying the power VddQ to half (18) output buffers 6#0 to 6#17 included in the synchronous SRAM shown in FIG. 12 or 14. Four VddQ pads P4, P11, P20 and P27 corresponding to four VddQ pins supply the power supply voltage VddQ to the output buffers 6#0 to 6#17 through a VddQ line L10. Thus, operations of the output buffers 6#0 to 6#17 are implemented.
In the read operation, however, all output buffers 6#0 to 6#35 simultaneously operate, to cause noise on the VddQ line L10. The relation between the situation of this noise and a malfunction is described with reference to FIGS. 18 and 19.
FIGS. 18 and 19 are timing charts for illustrating the problem of the conventional synchronous SRAM through generation timing of noise in the read operation. The cycle (clock cycle) of the clock signal CLK is 100 MHz in FIG. 18 and 200 MHz in FIG. 19. The access time of a standard synchronous SRAM is about 3 ns from rise of the clock signal CLK. In other words, large noise originates in the power VddQ in about 3 ns from the rise of the clock signal CLK.
When the power VddQ for the output buffer is used also for the input buffer 90, therefore, the input buffer 90 may malfunction or the operation thereof may be retarded while the power VddQ is noisy.
When the operating frequency is about 100 MHz, the input signal changes after the noise on the power VddQ is suppressed to some extent as shown in FIG. 18, to cause no problem in operation.
When the operating frequency approaches 200 MHz, however, the input buffer 90 processes the input signal while the power VddQ is noisy, as shown in FIG. 19. In the conventional structure, therefore, a problem in operation arises when the operating frequency is increased.
FIG. 20 shows another input buffer 95 employed for the synchronous SRAM. The input buffer 95 includes PMOS transistors TP5 and TP6 and NMOS transistors TN5 and TN6. The transistors TP5 and TN5 are serially connected between power Vdd and a ground power source, and the gates thereof receive an input signal. The transistors TP6 and TN6 are serially connected between the power Vdd and the ground power source, and the gates thereof are connected to a node N5 between the transistors TP5 and TN5. A signal from a node N6 between the transistors TP6 and TN6 is input in an internal circuit (not shown).
The input buffer 95 receives an input signal of the CMOS level of 2.5 V directly in a CMOS inverter supplied with the power Vdd. The input buffer 95 is supplied with no power VddQ, dissimilarly to the input buffer 90. Therefore, the input buffer 95 is resistant against noise originating in the power VddQ due to operation of an output buffer.
When the input signal is at the high level of 2.5 V, however, the PMOS transistor TP5 is not completely turned off, to disadvantageously result in flow of a through current. When the input signal is 1.8 V, a larger through current flows.
In the structure of the type 1 pipelined burst SRAM mainly employed at present or the synchronous network SRAM regarded as the main advanced semiconductor integrated device, therefore, it is difficult to increase the operating frequency.
A type 2 pipelined burst SRAM supplies power to an input circuit and an output circuit independently of each other. FIG. 21 shows pin arrangement of the type 2 pipelined burst SRAM. In the type 2 pipelined burst SRAM, VddI pins (thirty-eighth, forty-third, eighty-seventh and ninety-fourth pins), VddQ pins (fourth, eleventh, twentieth, twenty-seventh, fifty-fourth, sixty-first, seventieth and seventy-seventh pins) and Vdd pins (fifteenth, forty-first, sixty-fifth and ninety-first pins) are so arranged as to supply power VddI to an input buffer, power VddQ to an output buffer and power Vdd to an internal circuit respectively. In this case, the input buffer and the output buffer, individually supplied with the power VddI and the power VddQ respectively, can operate at a high frequency.
Fourteenth, sixteenth, sixty-fourth and sixty-sixth pins are data strobe output pins STRBA#, STRBA, STRBB and STRBB#, a ninety-third pin is a strobe clock input pin SCLK, an eighty-fourth pin is a reset input pin RESET #, and a ninety-sixth pin is a read latency selection input pin RDLAT4#.
However, the pin arrangement and the pin functions of the synchronous SRAM shown in FIG. 21 are different from those of the synchronous SRAMs shown in FIGS. 12 to 15. Therefore, the synchronous SRAM shown in FIG. 21 cannot be employed in place of the type 1 pipelined burst SRAM mainly employed at present or the synchronous network SRAM regarded as the main advanced semiconductor integrated device.
Accordingly, an object of the present invention is to provide a semiconductor integrated device guaranteed in stable operation regardless of the operating frequency while completely maintaining compatibility with the type 1 pipelined burst SRAM mainly employed at present or the synchronous network SRAM regarded as the main advanced semiconductor integrated device.
The semiconductor integrated circuit according to the present invention comprises an internal circuit, including a memory cell array, supplied with a first power supply voltage, an input circuit capturing a signal for executing a write/read operation of the memory cell array, an output circuit outputting data read from the memory cell array and a package, having 100 pins arranged on four side surfaces, enclosing the input circuit, the internal circuit and the output circuit, while a second power supply voltage is supplied to each of a fourth pin, an eleventh pin, a twentieth pin, a twenty-seventh pin, a fifty-fourth pin, a sixty-first pin, a seventieth pin and a seventy-seventh pin among the 100 pins, and the input circuit and the output circuit operate with supply of the second power supply voltage from different pins among the fourth pin, the eleventh pin, the twentieth pin, the twenty-seventh pin, the fifty-fourth pin, the sixtyfirst pin, the seventieth pin and the seventy-seventh pin.
According to the inventive semiconductor integrated device, therefore, power for an input system and that for an output system can be separated from each other while maintaining compatibility with pins of a conventional type 1 pipelined burst SRAM or synchronous network SRAM. Thus, the input circuit can process an input signal with no influence by noise originating from operation of the output circuit. Consequently, the input circuit can precisely operate also when an operating frequency is increased.
Preferably, the package is a quad flat package. In particular, 30 pins in total among the 100 pins, including the fourth pin, the eleventh pin, the twentieth pin and the twenty-seventh pin, are arranged on a first side surface of the package, and 30 pins in total including the fifty-fourth pin, the sixty-first pin, the seventieth pin and the seventy-seventy pin are arranged on a second side surface opposite to the first side surface.
In particular, at least any of the eleventh pin, the twentieth pin, the sixty-first pin and the seventieth pin is electrically connected with the input circuit. Alternatively, any of the fourth pin, the twenty-seventh pin, the fifty-fourth pin and the seventy-seventh pin is electrically connected with the input circuit.
According to the aforementioned semiconductor integrated circuit, therefore, a quad flat package can be employed for maintaining compatibility with the conventional synchronous SRAM.
A pin supplying the second power supply voltage, located on an end of either side surface of the package, is used as the power supply pin for the input circuit. Thus, the output circuit can operate at a high speed.
Preferably, the second power supply voltage is equal to a high potential level of each of the input in the input circuit and the output from the output circuit.
According to the aforementioned semiconductor integrated circuit, therefore, the power supply voltage for the input circuit and the output circuit can be set to the high potential level of the input in the input circuit and the output from the output circuit. Thus, compatibility with the conventional synchronous SRAM can be maintained while the input circuit can be brought into a structure suppressing a through current.
Preferably, the semiconductor integrated circuit further comprises a first line for connecting a pin for supplying the second power supply voltage to the input circuit with the input circuit and a second line for connecting a pin for supplying the second power supply voltage to the output circuit with the output circuit, and the first line and the second line are arranged in electrical isolation from each other.
According to the aforementioned semiconductor integrated circuit, the power supply line for the input circuit and the power supply line for the output circuit are completely isolated from each other, whereby the input circuit can process the input signal with no influence by noise originating from operation of the output circuit.
Preferably, the semiconductor integrated circuit further comprises a supply node for supplying an internal power supply voltage to the internal circuit and a voltage-down circuit stepping down the first power supply voltage in response to the potential difference between a node receiving a reference voltage and the supply node, and the node receiving the reference voltage is connected with a pin supplying the second power supply voltage to the input circuit.
In particular, the voltage-down circuit includes an operational amplifier detecting the difference between the reference voltage and the internal power supply voltage and a transistor electrically connecting a node receiving the first power supply voltage and the supply node with each other in response to an output of the operational amplifier.
According to the aforementioned semiconductor integrated device, the power supply voltage for the internal circuit can be stepped down with reference to the voltage received from the power supply pin for the input circuit. Thus, a stable power supply voltage for the internal circuit can be generated and it is possible to employ an advanced process having cost effectiveness.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.